Matlab+FPGA

This page is related to the FPGA Ethernet page: FPGA Ethernet
In recent years, more and more attention is focused on FPGA application. However, there are not all designers who know how to code in VHDL. In this page, two different methods are introduced on translating Matlab algorithms to VHDL.

System Generator is a high-performance DSP systems using rapid prototyping and implementation tools. It is the bridge between high-level system and Xilinx FPGA DSP, its role as shown in Figure 2. System Generator is available in MATLAB/Simulink environment for algorithm and system modeling, and generates the corresponding project, and then call the appropriate components in ISE simulation, synthesis, implementation and complete the configuration of the chip. System Generator is the indispensable bond throughout the development process.
 * Method 1: Simulink - System Generator **

Function of System Generator

System Generator and ISE software version must be matched, also with a suitable version of MATLAB to work properly. The System Generator 14.4, requires the following software environment: **Note**: the system environment variables must be set to XILINX ISE installation directory. Similarly, System Generator for popular third-party software also has a corresponding version requirements.
 * System Generator Requirement **
 * MATLAB version of MATLAB / Simulink R2012a or later. Note: MATLAB software installation path cannot have spaces.
 * The ISE version 14.4 or later, ISE Simulator version is the full version.
 * IP core library version of ISE IP 14.4 or later.
 * ModelSim simulation tools have at least version SE v6.4 and later.

In the Simulink environment, Xilinx module connected according to the system design features, and define the appropriate system parameters. Then convert Simulink models into executable models for hardware with System Generator. The system-defined parameters will be correspond to the hardware, and input and output ports. It will automatically complete synthesis, simulation and implementation. The development process is divided into four steps: floating-point algorithm development, fixed-point algorithms, hardware system design, and code optimization.
 * System Generator Workflow **

The progress of converting algorithms to VHDL with System Generator consists of the following steps:

Step 1:Floating-point algorithm development: use MATLAB software and provided toolkit to quickly complete floating-point arithmetic in the development, validation and performance evaluation. By means of Simulink, designer can quickly prototyping and model analysis.

Step 2:Fixed-point algorithm: change the floating-point algorithm to fixed-point logic with the use of Xilinx devices AccelDSP.

Step 3:Hardware System Design and Implementation: define detailed hardware using Xilinx IP architecture, and use System Generator for DSP to divide between the design of programmable devices and the coprocessor.

Step 4:Code Optimization: use ISE RTL design environment to generate optimized FPGA design that is advanced applications. This requires designers not only be familiar with the structure of the algorithm, the bottleneck, but also proficient in RTL design. For general design, if the hardware has enough memory, coupled with the design cycle is short, designer can ignore this step.

Therefore, the typical development process shown as figure below, where System Generator automatically integrates for FPGA, simulates HDL code, and implements generated command files. Designer only needs to complete the final Simulink design and compare RTL output. The entire development process is complete in the visualization environment. This example uses the System Generator to make a Xilinx FPGA moving LED. Step 1:Create mdl file Click File - New - Model in Simulink Library Browser, create a new mdl project as moving_light.mdl. **Note**: In the middle part of Gateway In and Gateway Out is FPGA design part to be achieved for DSP. The use of blockset must be in Xilinx Blockset and Xilinx Reference, so that System Generator is allowed to generate combined code.
 * System Generator Example **

**Gateway In**: it only uses as system reset, and the definition type is Boolean. Output is connected to other reset needed frequency module and Single Port Ram module. Sample period setting is according to requirement, and it generally set to 1 if the problem does not involve multi-rate.

**Single Port RAM**: eight output states for moving LEDs are stored in Single Port RAM. Initial value vector of the data type is not defined in the figure below. Its type is consistent as the default input data in RAM (UFix_8_0: unsigned fixed-point, bit width is 8, 0 means no decimal places). In this case the number of RAM Initial value vector has been written in advance, so enter 0 in the input write enable. The input data is 0 only plays the role of defining data type in RAM. By controlling Addr (address) to get desired output.


 * Counter ** : it used in performing operations like multiply-accumulate should always be reset using a combination of user reset.

Save thee mdl file after testing algorithm. Double-click on the System Generator block. It will pop up the dialog box shown below, change the default Part and type of chip, and package need to be matched with the FPGA chip on the board. Choose VHDL for Hardware description language. Create interface document and Create TestBench have same results as in the wave Scope. Click after checking. After waiting five minutes it will produce HDL code path in the netlist in the current directory. (If after doing large projects, the waiting time will be longer.
 * Step 2:Generate HDL code **

Double -click the generated moving_light_cw.xise in of the project file. It open as shown below. Click on the selected design in the moving_light_cw.xise, click Synthesize-XST comprehensive generated code. After Synthesize process if it is correct, click User constraints in the I / O Pin Planning for pin assignments.
 * Step 3:Program in ISE **

Refer to Xilinx Virtex 4 FPGA Board Technical Manual, assign the appropriate pin to the gateway_in, Gateway_out and clk(clock). Save and exit back to the ISE PlanAhead.
 * Note ** : Scalar ports of ce is used for debugging multi-rate, it is not important in this example.

In ISE double-click Implement Design, Generate Programming File and Configure Targe Device. After clicking Configure Target Device, it may pop-up a warning, just ignore it. And then it will automatically open the ISE iMPACT. Create a new project in iMPACT and click OK for pop-up dialog. Download the generated bit file to xc4vsx35 as below. After verifying the FPGA, it can be observed that the LED shifts to left every one second.
 * Step 4:Download to FPGA board **

Due to the order of magnitude performance improvement when running high-throughput, high-performance applications, algorithm designers are increasingly using FPGAs to prototype and validate their innovations instead of using traditional processors. However, many of the algorithms are implemented in Matlab because of the simple-to-use programming model, rich analysis and visualization capabilities. When targeting FPGAs or ASICs these Matlab algorithms have to be manually translated to HDL. The progress of converting Matlab algorithms to VHDL consists of the following steps:
 * Method 2: **** Matlab - HDL Coder **

Step 1:Model the algorithm in Matlab: use Matlab to simulate, debug and optimize the design. Step 2:Generate HDL code: automatically create HDL code for FPGA. Step 3:Verify HDL code: reuse the designed Matlab test bench to verify the generated HDL code. Step 4:Create and verify FPGA prototype: implement and verify the design on FPGAs.

Matlab code is procedural and can be highly abstract; it can use floating-point data and has no notion of time. Complex loops can be inferred from matrix operations and toolbox functions. Implementing Matlab code in hardware involves some unique challenges list below:


 * Converting floating-point Matlab code to fixed-point Matlab code with optimized but widths suitable for efficient hardware generation.
 * Identifying and mapping procedural constructs to concurrent area- and speed-optimized hardware operations.
 * Introducing the concept of time by adding clocks and clock rates to schedule the operations in hardware.
 * Creating resource-shared to implement expensive operators like multipliers and for-loop bodies.
 * Mapping large persistent arrays to block RAM workflow automation.

This algorithm, implemented in Matlab, enhances image contrast by transforming the value in an intensity image so that the histogram of the output image is approximately flat.
 * HDL Coder Example**
 * Step 1:Create a Matlab algorithm [[file:mlhdlc_heq.m]] **

There is the test bench that verifies that the algorithm works with an example image. **Test Result**
 * Step 2:Create a Matlab Test Bench [[file:test_image.m]] **
 * Step 3:Set up an HDL Coder Project **
 * Create a new project named imageMatlab: File -> New -> Code Generation Project. Choose HDL Code Generation as Type.
 * HDL Coder creates the project, imageMatlab.prj, in the local working folder, and, by default, opens the project in the right side of Matlab workspace.
 * On the project Entry Points tab, under Matlab Function, click Add Matlab function.
 * In the Add Files dialog, select mlhdlc_heq.m and click Open. HDL Coder adds the file to the project.
 * On the project Entry Points tab, under Matlab Test Bench, click Add Matlab test Bench.
 * In the Add Files dialog box, select test_image.m and click Open. HDL Coder adds the rest bench file to the project.

In the Workflow Advisor left pane, select Code Generation from the MATLAB to HDL Workflow folder. On the Target tab, select Generate HDL test bench. HDL Coder generates VHDL code and provides links to this code and to a resource utilization report. **Note**: You can use the Target, Coding Style, Clocks and Ports, Test Bench, and Optimizations tabs to set code generation options. For more information, see the HDL Coder Workflow Advisor reference.
 * Step 4: Create Fixed-point Versions of the Algorithm and Test Bench **
 * Click the project Build tab. On the Build tab, click Advisor button to open HDL Coder Workflow Advisor.
 * Select the Verify Floating-Point Design task and click the Run Button.
 * Select the Propose Fixed-Point Type task. The advisor displays the Basic Settings tab. Click Run button in Advanced Settings.
 * Select and run Generate Fixed-Point Code.
 * Select and run Verify Fixed-Point Design.
 * Step 5:Generate HDL Coder **