FPGA+Ethernet

This page is related to the Matlab FPGA page: Matlab FPGA
The Ethernet Statistics core provides a user configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx Ethernet Media Access Controller(MAC) products. The core supports VHDL design environment. The Ethernet Statistics core is fully configurable using the CORE Generator software, which provides a graphical user interface (GUI) for defining parameters and options.


 * MAC Type ** : depending on the target XilinxFPGA architecture.

**Embedded TEMAC**: the Embedded Ethernet MAC is selected Virtex 4 device.

**Number of Statistic**s: the number of statistics can range from 20 to 64.

The Ethernet Statistics core is pre-synthesized and delivered as a Xilinx NGC netlist. The Ethernet Statistics core is pre-synthesized and delivered as a Xilinx NGC netlist, shown as shaded area in figure above.
 * Statistics Width ** : the width of the statistics can be selected from either 32-bit (using a single-block RAM in Virtex 4 FPGA architectures) or 64-bit (which requires two block RAMs in Virtex 4 architectures).
 * Statistics Clear on Rest ** : after selecting, extra logic is included to ensure all counters rest to zero at a system rest otherwise the counters maintain their previous values and only rest to zero when the maximum count value is reached.

The figure below illustrates an expanded diagram of the statistics. It shows input increment signals arriving from the vector decoder via an increment_vector bus. There is an increment bit for each counter; a toggle on a specific increment bit causes the corresponding counter to increment.

Within the core the current counter values are stored in Dural Port RAM. In response to toggles on the increment_vector signals, the individual counter values are read out of the dual port memory, incremented, and written back. This operation occurs on port A of the dual port memory. The statistics counters will wrap around when they reach their maximum value and they cannot be reset.

Port B of the dual port memory is reserved for the Management Interface which is free to read the current statistic values at any point in time. Each specific counter can be individually addressed. This Management Interface can either be shared with that of the chosen MAC, or used separately.

The f igure below shows the pinout of the Ethernet Statistics core.

The figure below shows the whole Ethernet design module.